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Pipeline_ MTS_Platform Architect

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Pipeline_ MTS_Platform Architect in Others new

  • Pure Storage
  • Full time
  • Email
  • Bengaluru, India

Responsibilities

  • Own platform software architecture for FlashArray and FlashBlade NPI programs from concept and ERD/PRD review through bring-up, validation, manufacturing handoff, and GA.
  • Define platform security architecture covering root of trust, secure boot, firmware resilience, TPM, measured boot, device identity, attestation, encryption, and signing workflows.
  • Extend the secure boot chain across firmware, bootloaders, the Linux kernel, Purity software, BMCs, NICs, HBAs, and drives.
  • Drive post-quantum cryptography readiness and alignment with OCP Security/SAFE, NIST SP 800-193, and NIST SSDF.
  • Architect firmware update, manufacturing provisioning, RMA, re-provisioning, and non-disruptive hardware upgrade flows.
  • Lead hardware bring-up and debugging for CPUs, chipsets, PCIe switches, NICs, and add-in cards while partnering with silicon, ODM, and JDM vendors.
  • Shape unified chassis manager, HAL, and BMC management layers across FlashArray and FlashBlade.
  • Review hardware designs, ERDs, and requirements to ensure platform software, diagnostics, and manageability are designed in from the outset.
  • Own root-cause analysis for complex platform, boot, and security escalations from internal testing through customer field issues.
  • Author design documents and architectural reviews, establish organizational standards, and mentor senior engineers across distributed teams.

Requirements

  • 15+ years of experience in platform, system, or firmware software for servers, storage, networking, or enterprise systems.
  • Proven experience serving as technical lead or architect for multiple NPI programs from bring-up through production.
  • Hands-on expertise with UEFI Secure Boot, hardware root of trust, TPM 2.0, measured boot, code signing, and key-management workflows.
  • Strong understanding of x86 boot flows, BIOS/UEFI, bootloaders, Linux kernel boot, BIOS vendors, and silicon reference code.
  • Knowledge of BMC and out-of-band management protocols including IPMI, Redfish, PLDM, MCTP, and SPDM.
  • Knowledge of PCIe Gen5/Gen6, I2C/SMBus, SPI, eSPI, CPLD/FPGA interactions, and CPU/NUMA architecture.
  • Strong Linux systems programming and kernel/driver experience, with expert C and proficiency in Python and shell.
  • Ability to debug across hardware and software boundaries using JTAG, logic and protocol analyzers, serial consoles, crash dumps, and boot logs.
  • Experience working directly with silicon vendors, ODM/JDM partners, and manufacturing teams.
  • Bachelor’s or higher in Computer Science, Computer Engineering, or Electrical Engineering.
  • Preferred qualifications include experience with Intel PFR, Caliptra, OpenTitan or similar roots of trust; PQC algorithms and migration; Common Criteria/FIPS certification; OCP standards; ARM-based platforms; and storage.
  • Ability to lead and influence distributed teams through technical credibility without direct authority.

Benefits

  • Flexible time off, wellness resources, and company-sponsored team events.
  • Growth and development support, employee resource groups, and an inclusive workplace.
  • Global collaboration across teams in Bengaluru, Silicon Valley, and Prague.
  • Candidates with disabilities may request accommodations throughout the hiring process.

Pure Storage

Pure Storage (NYSE: PSTG) uncomplicates data storage, forever. Pure delivers a cloud experience that empowers every organization to get the most from their data while reducing the complexity and expense of managing the infrastructure behind it. Pure’s commitment to providing true storage as-a-ser...

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