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Principal FW/SW Engineer

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Principal FW/SW Engineer in Canada

  • Astera Labs
  • Full time
  • Email
  • Toronto

Responsibilities

  • Own the embedded firmware stack from hardware abstraction and device drivers through management interfaces, diagnostics, and customer-facing APIs.
  • Design firmware for adaptive equalization, gain control, calibration, link training, PLL/CDR feedback, thermal management, and device telemetry.
  • Architect control algorithms, state machines, and tuning flows for analog and high-speed interfaces across process, voltage, and temperature variation.
  • Define software quality gates, validation criteria, and release practices from pre-silicon planning through production deployment.
  • Debug Ethernet configurations, link states, and failure modes across Layer 1 PHY, SERDES, FEC/PCS, MAC, retimer, and gearbox components.
  • Investigate register accesses, embedded SDK behavior, link state machines, telemetry, logs, and hardware measurements to identify root causes and deliver fixes.
  • Develop test plans, automate characterization flows, and verify firmware across corner cases and product configurations.
  • Support customer bring-up, field issue triage, and deployment readiness with applications, platform, silicon, systems, and validation teams.
  • Set technical direction, lead architecture and tradeoff discussions, and balance performance, code size, maintainability, and time to market.
  • Lead design reviews, implementation, code reviews, and difficult debug efforts; mentor engineers and contribute to recruiting, onboarding, and technical development.

Requirements

  • Bachelor’s degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field.
  • 8–12 years of experience developing embedded firmware or software for resource-constrained systems, with ownership from architecture through production.
  • Strong embedded C/C++ skills and deep knowledge of microcontroller architecture, memory-mapped peripherals, interrupt handling, and bare-metal firmware.
  • Hands-on experience with Ethernet or high-speed connectivity devices such as Layer 1 PHYs, SERDES, retimers, gearboxes, NICs, or switches.
  • Solid understanding of physical-layer behavior, link state machines, register-level debugging, and hardware/software integration.
  • Experience with feedback systems, adaptive algorithms, calibration, or tuning of analog or mixed-signal subsystems.
  • Proficiency with Microsoft-based development environments and Linux command-line tools, including GCC or Clang, Make, Bash, GDB, and Git.
  • Clear written and verbal communication and systematic debugging skills in a fast-moving environment with ambiguity.
  • A master’s degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field is preferred.
  • Python experience for test automation, debug tooling, data analysis, or lab workflows and hands-on experience with Jenkins and CI/CD infrastructure are preferred.
  • Preferred experience includes mixed-signal systems, analog signal paths, retimer or gearbox firmware, SDK/API development, optical or pluggable optics, high-speed copper connectivity, Ethernet PHY subsystems, FEC, PMA, signal-integrity analysis, lab equipment, FPGA emulation, pre-silicon validation, RTOS, device drivers, coroutines, mentoring, or recruiting.

Benefits

  • Full-time remote role located in Toronto or Ottawa, Ontario.
  • Occasional travel to the San Jose headquarters, approximately twice per year, is required for chip bring-up and project coordination.
  • The role may be eligible for a discretionary bonus, incentives, and benefits.

Astera Labs

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform int...

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